------------------------------------------------//库声明
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

------------------------------------------------//实体定义
entity div_even is
generic(data_width : integer := 20 );
port
(   fpshu  : in std_logic_vector(data_width - 1 downto 0);
    clk_in : in std_logic;
   clk_out : out std_logic
	     );
end entity div_even;
 
------------------------------------------------//结构体定义 
architecture behave of div_even is

------------------------------------------------//信号量定义
signal clk_temp : std_logic;
signal  count_1 : std_logic_vector (data_width - 1 downto 0);

begin
 
------------------------------------------------//进程1，计数 
    process(clk_in)
    begin
        if clk_in'event and clk_in = '1' then
            if count_1 < (conv_integer(fpshu) - 1) then
                count_1 <= count_1 + 1;
            else count_1 <= (others => '0');
            end if;
        end if;   
    end process;

------------------------------------------------//进程2，比较输出
    process(count_1)
    begin
        if count_1 < (conv_integer(fpshu))/2 then
            clk_temp <= '1';
        else clk_temp <= '0';
        end if;
    end process;

------------------------------------------------//赋值	 
    clk_out <= clk_temp;
	 
end architecture behave;